XJCO1212 Computer Processors - Assignment: From Truth Tables to Circuits
School of Computing: Assessment brief
1. Assignment guidance
Your task is to design and implement a circuit in hdl which takes two 2-bit numbers as input and produces a 3-bit output.
The circuit has 6 inputs (?1 , ?0 ,A,B,C,D) and 3 outputs (E,F,G). The function of the circuit is determined by two of the inputs ?1 and ?0 .
2. Assessment tasks
The truth tables below define the operation of the circuit for each combination of ?1 and ?0 . ?1 , ?0 = (0,0) FZero A B C D F G 0 0 0 0 1 1 0 0 0 1 1 0 0 0 1 0 0 1 0 0 1 1 0 0 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 0 0 1 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 1 0 0 1 1 0 0 1 1 1 1 0 1 1 0 1 1 1 0 0 1 1 1 1 1 0 0
?1 , ?0 = (0,1) FOne A B C D F G 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 0 1 0 1 0 1 1 0 0 0 0 1 1 1 0 1 1 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 1 0 1 0 1 1 1 0 1 1 0 0 0 0 1 1 0 1 0 1 1 1 1 0 1 0 1 1 1 1 1 1
?1 , ?0 = (1,0) FTwo A B C D F G 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 0 1 1 1 1 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 1 1 1 1 0 0 0 1 0 1 0 0 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 ?1 , ?0 = (1,1) FThree A B C D E F G 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 1 1 0 1 1 0 1 0 0 0 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 1 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 1 1 1 0 1 0 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 1 1 0
a) Using Karnaugh maps derive the minimum Boolean expression for each of the outputs in each of the truth tables. Upload a copy of your Karnaugh maps and derived Boolean expressions to Gradescope. b) Implement the logic circuit for each output in a separate hdl files and test each one to confirm it produces the required output. The input/output names must be the same as they are in the truth table. You must only use the built-in AND, NAND, OR, NOR, NOT, Mux or DFF chips. c) For each of the four truth tables combine the circuits for the outputs together into one hdl file to produce one circuit for each truth table and test it produces the required output for that truth table. These should be named FZero, FOne, FTwo, FThree You must only use the built-in AND, NAND, OR, NOR, NOT, Mux or DFF or Mux chips. The test files provided (.tst and .cmp) can be used to test each output of a chip. For example FZero1.tst tests the F output of the chip FZero.hdl and FZero2.tst tests the G output of FZero.hdl. [13 marks] d) Combine all four circuits into one circuit which takes all six inputs and test it to ensure it produces the correct output depending on the value of the inputs ?1 and ?0 . Call the chip FALL. You can test this chip using FALL.tst but may wish to create further tests before submission. You must only use the built-in AND, NAND, OR, NOR, NOT, Mux or DFF chips.
[4 marks]
Stretch Activity
e) Adapt the circuit so that it can combine a sequence of operations defined by different values for ?1 and ?0 by enabling the outputs ?? and ?? to be used as the next inputs for ??+1 and ??+1 . You should also add a further input (Load) which when set to 1 will enable you to load inputs to ?? and ?? at the start and during the sequence if required. This should allow you to evaluate expressions such as X+Y+Z or X-Y as well as logical operations such as NOT(X OR Y) where X,Y and Z are all 2-bit binary numbers.
Call this chip FSEQ. You can test this chip using FSEQ.tst but may wish to create further tests before submission.
You must only use the built-in AND, NAND, OR, NOR, NOT, Mux or DFF chips.
[8 marks] [Total 25 marks]
3. General guidance and study support
Tools required to complete the hardware simulation are provided on Minerva under Learning Resources: Software. Support will be available during lab classes. Please ensure all your chips work with the test files provided and use the names provided in this sheet. Do not alter the format of these test files in any way. You are of course welcome to build your own or add to these. Ensure the files you upload pass the submission tests provided on Gradescope. These are not necessarily the same tests as those that will be used to grade your submission.
4. Assessment criteria and marking process
This coursework will be automatically marked using Gradescope. Feedback will be provided through Gradescope and example solutions discussed in class. Each chip for parts (b), (c) and (d) will tested against the full truth tables. Each test is worth one mark. No marks will be awarded for tests which fail, use chips other than those listed or for which the correct Karnaugh map or Boolean expression is not provided in Gradescope. Part (e) will be evaluated by testing it on four sequences of functions of various lengths (2 marks each)
5. Presentation and referencing
Submitted code should provide suitable comments where possible.
6. Submission requirements
Links to submit your work can be found on Minerva under Assessment and feedback/Submit my work. Upload a copy (scanned, photo, etc.) of your Karnaugh maps and Boolean expressions to Gradescope using the link to Coursework 1-Part a) Upload Karnaugh Maps and Boolean Expressions in Minerva. Submit only your hdl files either individually or as one zip file to Gradescope using the link to Coursework 1-Parts (c-e) in Minerva. The files should be FZero.hdl, FOne.hdl, FTwo.hdl, FThree.hdl, FALL.hdl and FSEQ.hdl This will test your submission against some tests to check it is format correctly etc.
