Computer Systems Architecture 2022/23 Laboratory Exercise - Cache controller simulator
In this laboratory exercise you will write a C program to simulate the operation of a direct mapped cache controller on an embedded system. You will use your simulator to analyse the impact of cache memory size, cache memory block size and cache write policy on the performance of the embedded system when executing a bubble sort algorithm.
You will work individually on this laboratory exercise; submitting a C program, a results file and an individual report.
2. Embedded system memory architecture
|The embedded system is interfaced to a 256 Ki x 16-bit external data memory using a 20-bit address bus and a 16-bit data bus. The embedded system contains a direct mapped cache controller for data accesses, and the controller can be configured in one of the 16 modes listed in Table 1. Mode ID||Cache block size (16-bit words)||Number of cache blocks||Cache size (16-bit words) 128||Write Policy|
Table 1. Cache controller configuration modes (WAWB Write Allocate/Write Back WAWT Write Allocate/Write Through)
3. Memory trace files
You are provided with a memory trace file, bubble_sort_trace_nnn.trc, that contains the addresses of all the read and write memory accesses generated by the CPU of the embedded system when sorting an array of 1500 random 16-bit values using a bubble sort algorithm. The memory trace file only records array accesses, as all other variables can are stored in processor registers.
The document, Generating Trace Files, describes how the memory trace files are generated, and provides a simplified example using the bubble sort algorithm. Each student has their own unique trace file to analyse. You can find the value of the 3-digit ID number nnn identifying your unique trace file in the TRACE FILE ID column in Blackboard Gradebook.
4. Cache controller simulator
Write a structured program in C to simulate the operation of the data cache controller in the embedded system. You may wish to first write a program to simulate the configuration where the cache has 8 blocks, a block size of 16 16-bit words and uses a Write Allocate/Write Back write policy. You can then enhance this program to simulate the other cache controller configuration modes shown in Table 1.
The cache controller simulator must be written as a single source file using ANSI standard C. The program must be suitable to be run from a terminal window without requiring user input and provide its formatted output to the terminal window.
The program must not be stored in a software repository, such as GitHub, with shared access.
The program must include a header which includes your name and student ID number. The program must be clearly commented and use descriptive function and variable names. The bubble sort algorithm presented in Appendix A is a good example of how to comment a program.
It is strongly recommended that you construct a software flowchart for the operation of the cache controller, and then directly code this in C.
The simulator must output its results in the comma separated variable (CSV) format described below. A sample set of results are presented in Appendix B. trace_file_name, mode_ID, NRA, NWA, NCRH, NCRM, NCWH, NCWM
trace_file_name The name of the trace file being analysed (without the folder path) mode_ID The ID number of the cache controller configuration 16) NRA Total number of read accesses to the external memory NWA Total number of write accesses to the external memory NCRH Number of cache read hits NCRM Number of cache read misses NCWH Number of cache write hits NCWM Number of cache write misses
The mode_ID, NRA, NWA, NCRH, NCRM, NCWH and NCWM values should all be formatted as unsigned integers.
5. Testing your simulator
A small test memory trace file, test_trace.trc, has been provided to help you test your trace file read function. As the memory trace files are ASCII text files with a very simple structure, you can create your own trace files to test your cache simulator. The document, Testing your Cache Controller Simulator, describes one approach to systematically testing your implementation of the cache controller simulator.
6. Cache controller performance simulations
For each of the configuration modes listed in Table 1, you should simulate the performance of the cache memory controller for the bubble sort algorithm using your allocated memory trace file.