Computer Architecture - Project 1: MIPS simulator
Project 1
Computer Architecture: Spring 2024
You are not allowed to take or give help in completing this project. No late submission will be accepted. Please include the following sentence on top of your source file: On my honor, I have neither given nor received unauthorized aid on this assignment.
In this project you will create a simple MIPS simulator which will perform the following
two tasks:
⚫ Load a specified MIPS text file1 and generate the assembly code equivalent to the
input file (disassembler). Please see the sample input file and disassembly output.
⚫ Generate the instruction-by-instruction simulation of the MIPS code (simulator). It should also produce/print the contents of registers and data memories after execution of each instruction. Please see the sample simulation output file.
You do not have to implement any exception/interrupt handling during simulation for this project.
Instructions
For reference, please use the MIPS Instruction Set Architecture PDF (available from
class project1 webpage) to see the format for each instruction and pay attention to the
following changes.
Your disassembler/simulator need to support the two categories of MIPS instructions
shown in Figure 1.
The format of Category-1 instructions is described in Figure 2. If the instruction belongs to Category-1, the first two bits (leftmost bits) are always “01” followed by 4 bits Opcode. Please note that instead of using 6 bits Opcode in MIPS, we use 4 bits Opcode as described in Figure 3. The remaining part of the instruction binary is exactly the same as the original MIPS instruction set.
Please pay attention to the exact description of instruction formats and its interpretation in MIPS instruction set manual. For example, in case of J instruction, the 26 bit instruction_index is shifted left by two bits (padded with 00 at LSB side) and then the leftmost (MSB side) four bits of the delay slot instruction are used to form the four bits (MSB side) of the target address. Similarly, for BEQ, BLTZ and BGTZ instructions, the 16 bit offset is shifted left by two bits to form 18 bit signed offset that is added with the address of the delay slot instruction to form the target address.
If the instruction belongs to Category-2, the first two bits (leftmost two bits) are always “11”. Then the following 4 bits serve as identification bits which are specified in Figure 4.
Instructions in Category-2 can be further divided into two sub-sets according to whether source2 is register or immediate. When the source2 is register, (“rd ← rs op rt”), the format is shown in Figure 5.
Sample Input/Output Fils
Your program will be given a binary (text) input file. This file will contain a sequence of 32-bit instruction words which begin at address "256". The final instruction in the sequence of instructions is always BREAK. Following the BREAK instruction (immediately after BREAK), there is a sequence of 32-bit 2's complement signed integers for the program data up to the end of the file. The NEWLINE character can be either “\n” (linux) or “\r\n” (windows). Your code should work for both cases.
Your MIPS simulator (with executable name as MIPSsim) should accept an input file (inputfilename.txt) in the following command format and produce two output files in the same directory: disassembly.txt (contains disassembled output) and simulation.txt (contains the simulation trace). You can hardcode the names of the output files. Please do not hardcode the input filename. It will be specified when running your program. It can be “sample.txt” or “t1.txt”. MIPSsim inputfilename.txt
Correct handling of the sample input file (with possible different data values) will be used to determine 60% of the credit. The remaining 40% will be determined from other valid test cases that you will not have access prior to grading. It is recommended that you construct your own sample input files with which to further test your disassembler/simulator.
The disassembler output file should contain 3 columns of data with each column separated by one
tab character (‘\t’ or char(9)). See the sample disassembly file in the class Project1 webpage.
1. The text (e.g., 0’s and 1’s) string representing the 32-bit data word at that location.
2. The address (in decimal) of that location
3. The disassembled instruction.
Note, if you are displaying an instruction, the third column should contain every part of the instruction, with each argument separated by a comma and then a space (“, ”).
The simulation output file should have the following format.
* 20 hyphens and a new line
* Cycle: < cycleNumber > < tab >< instr_Address >< tab >< instr_string >
* < blank_line >
* Registers
* R00:< tab >< int(R0) >< tab >< int(R1) >...< tab >< int(R7) >
* R08:< tab >< int(R8) >< tab >< int(R9) >...< tab >< int(R15) >
* R16:< tab >< int(R16) >< tab >< int(R17) >...< tab >< int(R23) >
* R24:< tab >< int(R24) >< tab >< int(R25) >...< tab >< int(R31) >
* < blank_line >
* Data
* < firstDataAddress >:< tab >< display 8 data words as integers with tabs in between >
* ..... < continue until the last data word >
The instructions and instruction arguments should be in capital letters. Display all integer values in decimal. Immediate values should be preceded by a “#” symbol. Note that some instructions take signed immediate values while others take unsigned immediate values. You will have to make sure you properly display a signed or unsigned value depending on the context.
Because we will be using “diff –w -B” to check your output versus ours, please follow the output formatting. TA may not be able to debug in case of any mismatch. In other words, mismatches can be treated as wrong output.
The course project webpage contains the following sample programs/files to test your disassembler/simulator.
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⚫ sample.txt : This is the input to your program.
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⚫ disassembly.txt : This is what your program should produce as disassembled output.
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⚫ simulation.txt : This is what your program should output as simulation trace.
Submission Policy:
Please follow the submission policy outlined below. There can be up to 10% score penalty based on the nature of submission policy violations.
1. Please submit only one source file. Please add “.txt” at the end of your filename. Your file name must be MIPSsim (e.g., MIPSsim.c.txt or MIPSsim.cpp.txt or MIPSsim.java.txt). On top of the source file, please include the sentence: “/* On my honor, I have neither given nor received unauthorized aid on this assignment */”.
2. Please test your submission. These are the exact steps we will follow too.
o Download your submission from eLearning (ensures your upload was successful). o Remove “.txt” extension (e.g., MIPSsim.c.txt should be renamed to MIPSsim.c)
Please compile to produce an executable named MIPSsim.
▪ gcc MIPSsim.c –o MIPSsim or javac MIPSsim.java or g++ MIPSsim.cpp –o MIPSsim
o Please do not print anything on screen.
o Please do not hardcode input filename, accept it as a command line option.
o Execute to generate disassembly and simulation files and test with correct/provided
ones
▪ ./MIPSsim inputfilename.txt or java MIPSsim inputfilename.txt
▪ diff –w –B disassembly.txt sample_disassembly.txt
▪ diff –w –B simulation.txt sample_simulation.txt
