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SDSUCS480Operating SystemsL1 CacheScheduler

Assignment 02 Free Response Questions CourseNana.COM

Due: Beginning of the class, Oct 15th
Late due: Beginning of the class, Oct 17th CourseNana.COM

You must work on this assignment on your own. CourseNana.COM

Turning into Gradescope CourseNana.COM

Submit ONE PDF file with your answers in the order of the questions. Make sure the file contains your name and Red ID at the beginning! CourseNana.COM

Make sure to include the single examinee affidavit (refer to SingleExamineeAffidavit_NonProgrammingAssignment.docx in Canvas) at the beginning of your answer sheet. You must work on your own for this part. It would be a red flag if we find submissions from two students are with highly similar answers in multiple parts. Also as specifically mentioned in the Syllabus, posting questions to online platforms, and asking for help are considered plagiarism. Answers from online sources will be investigated during grading, particularly the AI chatbot platforms such as chatgpt, gemini, etc. CourseNana.COM

SINGLE EXAMINEE AFFIDAVIT CourseNana.COM

“I, the undersigned, promise that this assignment submission is my own work. I recognize that should this not be the case; I will be subject to plagiarism penalties as outlined in the course syllabus.” CourseNana.COM

Student Name: __________________ RED ID: __________________ Date: __________________ CourseNana.COM

Part I Questions (60 points) Each question is worth 10 points. CourseNana.COM

  1. A run-time profiling tool shows that a machine with more CPU cores often has better cache hit rate (i.e., more effective caching) than the one with less CPU cores, this is particularly true when running many applications concurrently: CourseNana.COM

    1. Explain why. Hint: consider the principles behind the caching mechanism and how context switches for concurrent executions could affect caching. CourseNana.COM

    2. Suppose the CPU cores have L1 cache per core, using a cache write through policy, can cache incoherency happen in the L1 cache, and why? CourseNana.COM

  2. Based on what was discussed in the class about the detailed steps in interrupt handling and system call execution, what are the similarities between handling an interrupt from a mouse click and handling a system call to read data from a persistent storage. CourseNana.COM

  3. A user program executes the following C code in a Linux virtual machine that runs on top of a type I hypervisor. Based on what was discussed in the class, describe how the code execution is carried out in detail by the VM user, VM kernel, hypervisor and hardware, particularly how the run-time conditions are handled (if there are any) between them. Hint: consider how the software interrupts (run time exceptions and system calls if there are any) are handled in a virtualized environment. Watch the lecture recording where we discussed the details of those scenarios. CourseNana.COM

    void *workerthread(void *arg) { CourseNana.COM

    char* message = (char *) arg; CourseNana.COM

    return NULL; } CourseNana.COM

    int main() {
    pthread_t thread_id; int *recordRes;
    CourseNana.COM

    char message[] = "Learning OS is awesome"; CourseNana.COM

    int result = pthread_create(&thread_id, NULL, &workerthread, (void*) message); CourseNana.COM

    printf(“%s”, message); CourseNana.COM

    *recordRes = result; } CourseNana.COM

  1. In a 32-bit system, the following function is invoked: CourseNana.COM

    int countBitMasks(int level, unsigned int *masks) CourseNana.COM

    where level is an integer with a value of 5, mask is a 32-bit unsigned integer pointer CourseNana.COM

    pointing at a memory address of 0xAC27, and the return value is an integer. Assume: CourseNana.COM

    1. Each integer or pointer occupies 4 bytes, i.e., 32 bits. CourseNana.COM

    2. The stack is used for passing data between the caller and callee, and right before CourseNana.COM

      invoking the function, the $SP register has a value of 0x7004. CourseNana.COM

    3. The calling convention pushes the arguments to stack in reverse order, and the CourseNana.COM

      caller reserves the space for the return value on the stack after pushing the return CourseNana.COM

      address to the stack. CourseNana.COM

    4. The very next instruction in the caller after the function invocation is at address CourseNana.COM

      0x103D. CourseNana.COM

    Based on the steps we discussed in the class for invoking a function call, show a table (or diagram) for the stack content from the current top of the stack right before the execution is transitioned to the countBitMasks function. Make sure to specify the address and value of each item on the stack, if the value is unknown, put unknown there. (Note the stack grows to the lower address space.) CourseNana.COM

  2. In a uniprocessor system, processes P0, P1, P2 are admitted for scheduling at the same time in that order, each process has a series of alternating CPU bursts and I/O bursts as follows: CourseNana.COM

    P0: 3ms (CPU), 5ms (I/O), 6ms (CPU)
    P1: 4ms (CPU), 7ms (I/O), 3ms (CPU), 1ms (I/O), 6ms (CPU) P2: 5ms (CPU), 2ms (I/O), 3ms (CPU)
    CourseNana.COM

    Show your steps to find the turnaround (completion) and wait times of all processes using the Round Robin scheduling algorithm with a time quantum of 3ms. CourseNana.COM

    For simplicity, assume context switch time and other overheads are comparatively negligible. Note: CourseNana.COM

    • Wait time is the wait time each process spends in the process READY queue. CourseNana.COM

    • Turnaround time = CPU bursts + I/O bursts + Wait time CourseNana.COM

    • Each process is accessing a separate I/O, when the process enters the next I/O CourseNana.COM

      burst, it will execute it immediately, this implies: CourseNana.COM

o During the CPU burst (execution) of a process, all blocked processes due to I/O CourseNana.COM

would be executing their respective current I/O burst at the same time. CourseNana.COM

You must show your steps by using the notation p (e, s, r) system below to track CPU execution of a process over the time: CourseNana.COM

e - total CPU burst time that has been executed for a particular process,
s - total system time passed from the beginning of executing first process,
r - the reason why the process is stopped along the execution (either suspended or completed) due to:
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  • i - process initiated an I/O, CourseNana.COM

  • c - process completed execution CourseNana.COM

  • t - time quantum expired during RR CourseNana.COM

  • For example: P0(10, 16, i) means total CPU burst time that has been CourseNana.COM

    executed for process P0 is 10ms, total system time passed is 16ms since the start of system executing, and process P0 is suspended due to entering an I/O burst. P1(5, 18, t) means total CPU burst time that has been executed for process P1 is 5ms, total system time passed is 18ms since the start of system executing, and process P1 is suspended due to quantum expiring before finishing the current CPU burst. CourseNana.COM

    Summarize your results for turnaround and wait times (after the completion of scheduling) in the following table: CourseNana.COM

Turnaround Time RR CourseNana.COM

Wait Time RR CourseNana.COM

P0
P1
P2 Average
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6. A non-preemptive scheduler is scheduling a system with 8 processes. The CPU has two cores executing processes P3 and P7. P12 and P27 (first in the queue) are ready to be executed. P8 (first in the queue) and P45 are waiting for input from the keyboard. P32 (first in the queue) and P6 are waiting to finish sending data over network. CourseNana.COM

  1. Show a scheduling queueing diagram for these processes (use a separate queue for each type of I/O). CourseNana.COM

  2. Assuming P3 is finishing its current CPU burst in 2ms and then will wait for keyboard input, and P32 is finishing its current network I/O burst in 2ms. When P3 completes the current CPU burst, draw arrows of where the processes would go for those who change queues. Label each process with its process state. CourseNana.COM

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