EECS2021 Computer Organization - Assignment2 RISC-V Simulator
EECS2021 Assignment 2: Due Date August 8th, 11:30 PM EST
Assumptions:
Submission: Online as explained in the Administration slides via: https://webapp.eecs.yorku.ca/submit/ppy
It is not mandatory to complete this assignment in a group (you can do it alone if desired). However, you can have groups of up to and including four students to collaborate on the assignment. It is expected that all the group members know all the portions of the work and will be able to reproduce it individually from scratch. Only one submission per group is allowed, and if two or more submissions are made, all members will get zero marks. In case of a group submission, the group should submit a file called "members.txt" with the exact format below:
This file should be submitted in a stand-alone format and should not reside inside a ZIP or compressed file. The format of the file is as below:
Line1: member1_eecs_username, member1_firstname, member1_last_name, member1_stundet_number, member1_email
Line2: same as line 1, but for the second member of the group
Line3: same as line 1, but for the third member of the group
Line4: same as line 1, but for the fourth member of the group
Note that the EECS_USERNAME should be in all lowercase and not contain any domain name or @ symbol.
Please note that you shall NOT submit a members.txt file if you submit the assignment individually.
Example: If the group has two members, we will have a text file with two lines called members.txt (all lowercase for the file name and plain text file; no MS Word document or RTF or PDF format!):
navidmo, Navid, Mohaghegh, 123456789, navidmo@yorku.ca
jillmo, Jill, Mohaghegh, 123456780, jillmo@yorku.ca
RISC-V Simulator: Similar to A1, you will be using Ripes as discussed in the class:
https://github.com/mortbopet/Ripes,
Your codes are well-documented via inline comments. You will submit a file called answers.pdf containing all your answers.
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Background:
Two-issue, statically scheduled processor benefits from the compiler to group two instructions into an "issue packet" to be executed in one clock cycle. This is in contrast to a single-issue instruction that only can execute one instruction in a single cycle. The issue packet sometimes is called a Very Long Instruction Word (VLIW). The compiler aims to remove all hazards by reordering instructions into issue packets. Sometimes compiler has to pad VLIW with no-operation instruction (e.g., NOP) if necessary. The compiler must bundle one ALU/branch instruction with one load/store instruction; if it cannot do that, it should use NOP to pad the unused instruction. Please refer to Figure 4.70 (page 344) of our textbook and read pages 342-347.
A reminder that Loop Unrolling is a technique to get more performance from loops that access arrays, in which multiple copies of the loop body are made and instructions from different iterations are scheduled together. Example is: for (int i=0; i < 1000; i=i+1) do_something(i); that can be unrolled to:
for (int i=0; i < 1000; i=i+5) {
do_something(i);
do_something(i+1);
do_something(i+2);
do_something(i+3);
do_something(i+4);
}
Also, make sure to read the example on page 346 of the textbook.
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Assignment 2:
Given the above background and the following code:
for(int i=0; i!=j; i=i+2) b[i]=a[i]–a[i+1];
We want to compare the performance of single-issue and multiple-issue processors, taking into account program transformations that can be made to optimize for 2-issue execution.
A compiler doing little or no optimization might produce the following RISC-V assembly code:
...
addi x12, x0, 0
jal ENT
TOP: slli x5, x12, 3
add x6, x10, x5
lw x7, 0(x6)
lw x29, 8(x6)
sub x30, x7, x29
add x31, x11, x5
sw x30, 0(x31)
addi x12, x12, 2
ENT: bne x12, x13, TOP
....
As seen above, we can assume that i is x12, j is x13, a is x10, b is x11, and x5, x6, x7, x29, x30, and x31 are temp registers.
Our two-issue, statically scheduled processor has the following properties:
1-One instruction must be a memory operation; the other must be an arithmetic/logic instruction or a branch.
2-The processor has all possible forwarding paths between stages (including paths to the ID stage for branch resolution).
3-The processor has perfect branch prediction.
4-Two instructions may not issue together in a packet if one depends on the other. (See page 342 of our textbook).
5-If a stall is necessary, both instructions in the issue packet must stall.
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Part A: Draw a pipeline diagram showing how the RISC-V code given above executes on the two-issue processor. Assume that the loop exits after two iterations.
Part B: What is the speedup of going from a one-issue to a two-issue processor? (Assume the loop runs 100,000 iterations).
Part C: Rearrange/rewrite the RISC-V code given above to achieve better performance on the one-issue processor. Hint: Use the instruction “beqz x13,DONE” to skip the loop entirely if j = 0.
Part D: Rearrange/rewrite the RISC-V code given above to achieve better performance on the two-issue processor. (Do not unroll the loop, however.)
Part E: Repeat Part A, but this time use your optimized code from Part D.
Part F: What is the speedup of going from a one-issue processor to a two-issue processor when running the optimized code from Part C and D?
Part G: Unroll the RISC-V code from Part-D so that each iteration of the unrolled loop handles two iterations of the original loop. Then, rearrange/rewrite your unrolled code to achieve better performance on the two-issue processor. You may assume that j is a multiple of 4. Hint: you may want to re-organize the loop so that some calculations appear outside and at the end of the loop. You may also assume that the values in temporary registers are not needed after the loop.
Part H: What is the speedup of going from a one-issue processor to a two-issue processor when running the unrolled, optimized code you created in Part G, assuming the two-issue processor can run two arithmetic/logic instructions together (e.g., the first instruction in a packet can be any type of instruction, but the second must be an arithmetic or logic instruction. And note that two memory operations cannot be scheduled at the same time.)
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