CS230 Computer Organization HomeWork #2 RISC-V Assembly
CS230 Computer Organization
HomeWork #2 (Due: 1 week)
Name: 張三 Student ID: 請寫學號
1. (1 Point) Please convert the following C code into RISC-V assembly code with a minimum number of instructions. When you are using the GPR registers, please use ther ABI names instead of their register numbers. Assume that the scalar values of i, num_eq and N are in registers t0, t1, and a2, respectively. Also, assume that registers a0 and a1 hold the base addresses of the array A, B respectively. The return value will be passed to the Caller by register a0.
Note: you should obey the register usage convention.
int count_eq_elems(int A[], int B[], int N)
{
int i, num_eq = 0;
for(i=0; i<N; i++) {
if(A[i] == B[i])
num_eq++;
}
return num_eq++;
}
Please write your assembly code in Table 1:
Table 1: List of instructions
Label | Instruction |
L1: | ADD t0, zero, zero |
L2: | ADD t1, zero, zero |
L3: | |
L4: | |
L5: | |
L6: | |
L7: | |
L8: | |
L9: | |
L10: | |
L11: | |
L12: | |
L13: |
2. (2 Points) Table 2 gives the RISC-V binary code and data (both in hexadecimal representation) for a program. Suppose PC=0x00400000 before program execution.
Table 2: Memory Content Before Program Execution
Address | Memory Content | |||||||
... | ... | ... | ... | ... | ... | ... | ... | ... |
0x00400000 | 0x0fc10517 | 0x00050513 | 0x00800593 | 0x008000ef | 0x00008067 | 0x00450293 | 0x00259313 | 0x006503b3 |
0x00400020 | 0x0272d863 | 0x0002a303 | 0xffc28e13 | 0x00ae4c63 | 0x000e2e83 | 0x01d35863 | 0x01de2223 | 0xffce0e13 |
0x00400040 | 0xfe0006e3 | 0x006e2223 | 0x00428293 | 0xfc000ae3 | 0x00000867 | ... | ... | ... |
... | ... | ... | ... | ... | ... | ... | ... | ... |
0x10010000 | 0x0000001c | 0x00000021 | 0x0000000c | 0x0000000b | 0x0000000f | 0x00000020 | 0x0000001b | 0x0000000a |
0x10010020 | 0x00000011 | 0x00000022 | 0x00000033 | 0x00000044 | 0x00000055 | 0x00000066 | 0x00000077 | 0x00000088 |
... | ... | ... | ... | ... | ... | ... | ... | ... |
a) (1 Point) Please translate the RISC-V binary code back into RISC-V assembly code in Table 3. The semantics of the first instruction AUIPC is: x10 = PC + (Imm20 << 12), and here Imm20 = 0x0fc10.
Table 3: Assembly Code of the Program
Label | Instruction |
L1: | AUIPC x10, 0x0fc10 |
L2: | |
L3: | |
L4: | |
L5: | |
L6: | |
L7: | |
L8: | |
L9: | |
L10: | |
L11: | |
L12: | |
L13: | |
L14: | |
L15: | |
L16: | |
L17: | |
L18: | |
L19: | |
L20: | |
L21: |
b) (0.5 Point) Please explain the functionality of the program (i.e., what it does), and give the updated data in the memory after the program execution in Table 4.
Table 4: Updated Memory Content After Program Execution
Address | Memory Content | |||||||
... | ... | ... | ... | ... | ... | ... | ... | ... |
0x10010000 |
|
|
|
|
|
|
|
|
0x10010020 |
|
|
|
|
|
|
|
|
... | ... | ... | ... | ... | ... | ... | ... | ... |
c) (0.5 Point) Are there any problem with this program? (Hint: related to issues of register usage convention).
3. (2 Points) Suppose we want to extend the single-cycle RV32I processor design with the AUIPC instruction (The semantics of the AUIPC is given in Question 2, and its encoding format can be referred to slide 61 in Lecture 4 ppt).
a) (0.5 Point) Do we need to add any new datapath component? If so, please describe the functionality of this new component, and describe its connections with other datapath components. Do we need to change the connections between any datapath components? If so, please describe the changes of connections.
b) (1 Point) Do we need to change the internal logic of any components? If the changed component is the ImmGen, please describe its detailed change by modifying the Excel tables provided together with this homework, and paste the screenshot of the Excel tables in this word document. For other changed component, you can simply describe the name of the component and the reason for changing it, without the need to give its detailed change.
c) (0.5 Point) Does AUIPC needs additional control signals? If so, please give their names and the datapath components that they control, as well as their usage. Please make change to the Truth Table for the PLA-based control logic by adding an addition table entry for auipc, and fill the values of its columns. If no additional control signal is needed, please just keep the last column empty.
Table 5: Changes to The Truth Table by AUIPC Instruction
Inst[31:0] | BrEq | BrLT | PCSel | BrUn | Op1Sel | Op2Sel | MemRW | RegW | WBSel | ImmSel | ALUctr | ? |
